Many modern semiconductor devices are composed of MOS (Metal-Oxide-Semiconductor) transistors and capacitors, in which the MOS transistors generally include a source, drain, and gate. The gate is sometimes called a gate stack because it may include a plurality of components, such as a gate electrode and an underlying gate dielectric. Sidewall spacers (also called spacers, or spacer layers) may be adjacent to the gate structure and usually include an oxide layer and a nitride layer component.
Spacers serve a number of functions in the formation of semiconductor devices. One function is to prevent the migration of dopants from the source and drain regions (and halo sections) upward into overlying layers (e.g., oxide layers such as the gate oxide layer, etc.). When dopants (e.g., boron) migrate upward it sets up concentration gradients in the underlying source or drain region, which can cause parasitic junctions that increase power consumption by the transistor. Spacers act as a barrier to this type of dopant migration.
The spacers may also serve to shield the gate electrode and halo sections of the transistor from subsequent dopant deposits, such as when the source and drain regions are being formed. The sidewall spacer layers covering the gate electrode and halo sections prevent dopants in the processing chamber from migrating into these regions as the source and drain regions are formed.
Conventional spacers are made by forming silicon oxide (SiO2) and/or silicon nitride (Si3N4) layers in low pressure chemical vapor deposition processes (LPCVD). In such LPCVD methods, a nitrogen-containing gas is reacted with a silicon-containing gas to deposit silicon-nitride on the substrate. LPCVD processes typically occur at operating temperatures of about 600° C. to about 800° C. At these temperatures, lighter dopants like boron can undergo significant thermal diffusion, cause the dopant region to expand or shift, and reducing the dopant concentration in the desired dopant region. Thermal diffusion can also cause dopant regions to move closer and even overlap with each other, causing short channel and punch-through effects. Thus, it is desirable to develop new, lower temperature spacer formation techniques that do not cause as much thermal diffusion of the deposited dopants.
Conventional sidewall spacers typically include a robust silicon nitride layer that can trap dopants like boron and prevent them from diffusing into the gate electrode, implant region, etc. Unfortunately, Si3N4 films have relatively poor dielectric qualities (k values of about 7.0 or more) which can increase the time constant (RC) for activating the gate electrode and slow the speed of the device. The dielectric qualities of the spacers may be improved by combining the high-k nitride layer with a lower-k silicon oxide film (e.g., k values of 4.0 or less) to lower the overall k value of the spacer. However, the silicon oxide film is relatively permeable to dopants like boron, limiting the extent to which SiO2 can substitute for Si3N4 in the spacer layers. Thus, there is a need for spacer layers with improved dielectric qualities and dopant diffusion characteristics. These and other issues are addressed by embodiments of the present invention.